Next-gen “Venice” EPYC CPU becomes first HPC product on TSMC’s advanced 2nm process
AMD has announced a major milestone in semiconductor innovation with the successful tape-out and bring-up of its next-generation AMD EPYC™ processor, codenamed “Venice,” on TSMC’s cutting-edge 2nm (N2) process technology. This marks the first high-performance computing (HPC) product in the industry to be developed on the N2 node.
The achievement reinforces AMD’s longstanding partnership with TSMC and demonstrates the companies’ ability to co-optimize new processor architectures with advanced manufacturing processes. “Venice” is set to launch next year and is expected to play a critical role in AMD’s data center CPU roadmap.
“Our deep collaboration with TSMC enables AMD to deliver leadership products that push the limits of high-performance computing.”
– Dr. Lisa Su, Chair and CEO, AMD
Additionally, AMD confirmed the validation of its 5th Gen EPYC CPU products at TSMC’s new Fab 21 in Arizona, a significant step toward scaling U.S.-based semiconductor manufacturing.
“TSMC has been a key partner for many years,” said Dr. Lisa Su, AMD Chair and CEO. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to deliver advanced technologies that will power the future of computing.”
TSMC Chairman and CEO Dr. C.C. Wei added, “Our collaboration with AMD on 2nm technology is driving new levels of performance, power efficiency, and yield.”
The Venice milestone further cements AMD’s position as a leader in high-performance and adaptive computing.
